Hey there, I happen to design electronics for construction and ag equipment. Construction and ag companies generally like to use the automotive EMC standards as a baseline so I am familiar with those standards and designing for them (ISO 11452 for radiated/conducted immunity, ISO 10605 for ESD, CISPR 25 for radiated/conducted emissions, ISO 16750 vehicle battery transients, ISO 7637 vehicle transients). I think it's helpful to walk through the required tests and determine what protection you need for each.

For the purposes of this post, I will assume that your "RTD signal conditioning" block consists of some sort of op amp circuitry or similar.

ESD

A suitably sized TVS diode is my go to. I usually choose it based on the data sheet calling out that it meets a particular ESD standard that is comparable to the one I am using. However, for analog lines you need to be careful about leakage current from the TVS diodes causing error in your analog reading. Maybe that's why you have the resistors in series? I haven't seen that before. Overall, set the clamping voltage of the TVS to something higher than your analog signal voltage so that you are guaranteeing an acceptable amount of leakage current from the TVS diodes for your application.

When you lay out your board, you need to put the TVS diodes as close as possible to the connector pins. make connections between the connector pins and the TVS diode pads as wide as possible, up to the width of the pads of the smallest component pad. Do not have any traces routed to your connector pins in between the connector and the TVS diode. You want the easiest path for ESD to go is directly to the TVS and shunted back out onto the cable connection. Any traces that need to be connected to the connector pins should be routed to the TVS pads. This is absolutely critical for passing the packaging and handling ESD test where the unit is unpowered and they hit the connector pins directly with +/-8kV.

Now, one more thing about ESD. You will likely have to pass a test where the unit is powered and ESD (+/-8kV direct, +/-15kV air typically) is applied to your device. Zaps are applied to locations that could touched when the unit is plugged in and powered. So, no TVS is really going to help you here because your connector pins are likely not exposed (since the connector is plugged into something else). The path for ESD to your board is not through the connector and thus you need to protect the board in other ways. This is where you need to either (a) ensure that any zaps applied to your electronics go around them and straight to ground (e.g. a grounded, metal housing) or (b) ensure that you have no exposed metal subject to the ESD test that is within 15-20mm of your electronics (use mechanical design to ensure nothing an be zapped that will be able to jump to your board). Why 15-20mm? Well, the dielectric strength of air is about 1kV/mm. With 15-20mm, you are ensuring that you have at least 15-20kV of isolation between the ESD gun and your board. Consequently, there is no path for ESD in that case. If you can't do that, then you are down to changing materials, adding shields, using "tortured path" mechanical design, or just simply having to deal with ESD on your board and the effects of that (bad!).

Immunity (i.e. protecting against injected noise)

Here you're likely looking protecting against noise at frequency ranges in the 1MHz to possibly 3GHz range. It depends on the company you are designing for usually. However, this is where you usually want to start off with a pi filter (cap - ferrite - cap) right after your TVS diode. A good bet is something like a 0.1uF cap - ferrite - 0.1uF cap. Whatever you do, you want to try and filter in the frequency range where the test will be done. One caveat here is that there are some standards (ISO 11452-4) where there is a bulk current injection test. It's a lot to get into, but generally you need to take special care in passing a BCI test if it is required.

Emissions

You have two circuit defenses against emissions. The first and best is to have ample decoupling and bulk capacitance on your board. Conduction emissions is a result of your board not having enough local charge storage and thus pulling high frequency currents across your power cables. This can also lead to radiated emissions. Two things are critical in providing this local storage. (a) You can't have too many bulk caps. Use many and ensure they are sprinkled about your board so that no IC is more than say 1-5mm away from bulk capacitance. (b) Decoupling caps need to be placed as close as possible to the VCC pins of each IC. 0.1uF is a good starting point. Keep traces very very short. Keep vias to ground and power planes directly off of the side of the cap, as close as possible to each other to keep the loop areas small. The more you do this, the more effective they will be. Multiple vias for each connection to the power and ground planes can be used to increase performance too.

The second circuit defense for emissions is the pi filter from the Immunity section above. That will help filter remaining emissions before it reaches the cables and outside world where emissions are measured. Conducted emissions is typically around 150kHz to 100MHz. Radiated emissions is typically higher, about 200MHz to 3GHz.

Board Layout

This is where EMC performance is made or lost. You need to be a complete stickler about your board layouts. Don't settle for bad practices in layout because they will be the thing that kills your EMC performance. I've mentioned a few layout related things already, but here's a couple more.

• Board stackup - I won't go into too much detail, but more layers = better performance. A 2 layer board is almost guaranteed to fail emissions testing. 4 Layer is a minimum. At my job, we use 6 layers as our standard. Your goal here is to tightly couple the signals to the planes by having small dielectric heights and the proper layer order.
  
• Component placement - Always filter at the periphery of the board. Keep all other components away from the connections to the board (13mm is a good rule of thumb here). Keep components at least 2mm away from the edge of the board. Keep sensitive analog circuits away from digital circuits (note that a digital trace can have return currents up to 50x the dielectric height away from the digital trace. A digital trace routed on an internal layer will reduce this to 3x. You want to ensure those high frequency return currents are not interfering with your analog circuits. Keep separation there but do not break up the ground planes. Thou shalt have one ground plane!
  
• Critical trace routing - Mentioned this above but route fast traces first and keep them away from the analogs. Use internal layers if you can. Never route a trace over a gap in the ground/power plane. Never route a trace over an area without ground/power (i.e. at the edge)
  
• Ground/Power Planes - Pull ground plane back at least 0.5mm from the edge of the board for avoiding manufacturability issues. Now, pull the power plane back another 0.5 to 2mm back from the edge of the ground plane to ensure that stray fields are contained on the board.
  
• Routing with layer transitions - Any time you switch layers and the trace now has a new reference plane, you need to provide a stitching cap or via to allow the return currents to make it to the new reference plane within, say, 1mm of the layer transition. An example of this would be a 4 layer board where a top layer trace goes through a via to the bottom layer. Where that happens, you want to add a decoupling cap (0.1uF) right there between the power and ground planes.
  
  These are the types of things you really want to take care about if you are serious about designing high quality boards for automotive. Henry Ott's book is a great resource that I feel can greatly help explain the above comments in much better detail than I can here.
  
  ​
  
  Good luck! Let me know if you have questions.
  
  ​

Strictly speaking in terms of bang for buck, I like Robert's courses. They are Altium-centric, of course, but the concepts he teaches will apply to any tool.

http://www.fedevel.com/academy

I highly recommend one book if you don't have it in your library, Henry Ott's EMC engineering...it served as a constant reference for me in the lab:

https://www.amazon.com/Electromagnetic-Compatibility-Engineering-Henry-Ott/dp/0470189304

These two are basically the EMC (electromagnetic compatibility) bibles.

https://www.amazon.com/Electromagnetic-Compatibility-Engineering-Henry-Ott/dp/0470189304/ref=sr_1_1?ie=UTF8&qid=1473423741&sr=8-1&keywords=henry+ott

and

https://www.amazon.com/Introduction-Electromagnetic-Compatibility-Clayton-Paul/dp/0471755001/ref=pd_sim_14_2?ie=UTF8&psc=1&refRID=NH25ENV6BABM8C93TMJA

Excellent work. Thanks for contributing to the open-source community.

As for your question about four layers vs. two: oof. That is a surprisingly complex question. Generally, I follow the rules of Henry Ott in his very useful textbook, Electromagnetic Compatibility Engineering. I can't personally say if going from four layers to two layers is going to work. My gut feeling is that it will. I just wanted to be sure when I was doing my design.

In that case, I'd recommend a companion text:

Controlling Conducted Emissions by Design (J Fluke)

Ott has some great books as well (the book on EMC):

Electromagnetic Compatibility Engineering

Noise Reduction Techniques in Electronic Systems

You may consider a hobbyists book to start with, something like this Eagle Book
or this user
But for the real details I recommend this book or similar

Besides knowing the tools you really only need to know Tx Line analysis and (Signal/Power) Integrity information. Which may be some of the most important details to PCB design in my very limited opinion.

My understanding is that placing the caps on the other side of the board isn't optimal, but will work, so long as you remember to keep the connections low inductance.

As for the value, it's partly determined by the frequencies you'll see in the circuit.

When considering the frequencies of the board it's best to look at periodic high frequencies, like clocks. But remember, because the clocks are "square waves" not sine waves there are a lot of higher order frequencies contained in them. Take the Fourier transform of a trapezoidal wave to see what I mean. These higher order frequencies are the ones you need to worry about.

0.1uF is good for circuits that are lower frequency, above 100MHz or so a lot of engineers will use 10nF or smaller caps for decoupling.

Check out a book on EMC for more information. [This] (http://www.amazon.com/Electromagnetic-Compatibility-Engineering-Henry-Ott/dp/0470189304/ref=sr_1_1?ie=UTF8&qid=1333128646&sr=8-1) one contains a lot of good information of board design.

Edit: One thing I think forgot to mention is that you should generally route power and ground first. If you're using planes on inner layers this is really easy, if not try to make a grid of power traces on one side and ground on the other. This is because each parallel connection you have that is far enough apart to minimize the mutual inductance will reduce the overall inductance. At it's limit this becomes a plane.

Once you have your power and ground routed then do the clocks, then the digital signals.

This does not address the issues with analog signals on the board, as they should be segregated from all digital circuitry and power supplies.