Reddit reviews SystemVerilog for Verification: A Guide to Learning the Testbench Language Features

There are two books that are decent

SystemVerilog for Verification and SystemVerilog for Design


I have found The Designer's Guide to VHDL by Peter Ashenden to be a god-send for learning VHDL from a language perspective. I have found nothing as good for SystemVerilog. Those two books I mentioned are close though.

My personal opinion is that SystemVerilog is cool, but frankly just an unmitigated shit-show of language design. They should be ashamed of how poor it is.

There is no concept of a standard library, and things that should be in a standard library are core language. Then there is this idea of a "Verification Methodology" like OVM and UVM, which are libraries, but they are glued into the core language through MACROS!!! MACROS!! I'm not kidding. It is almost comical how bad it is.
As I've said before. We need an open source simulator that can handle multiple language simulations, and then to replace this mess with something modern and awesome.


I would also suggest checking out this guys stuff http://syswip.com/. It is a little funny in some places, but it really helped me understand so of the approaches that a designer could take. The approach a UVM guy would take, is sadly, almost completely different than this. I don't think it is better though depending on what you are doing.

https://www.amazon.com/gp/aw/d/1461407141/

this book might help

System Verilog is just Verilog with OOP, I'd start learning about that first. I'd just get a older edition text book. We used this https://www.amazon.com/gp/aw/d/1461407141/ref=pd_aw_sim_14_1?ie=UTF8&psc=1&refRID=VFTMYSQVKP7Z9GB91S86

What are you shooting for?

RTL Modeling with SystemVerilog for Simulation and Synthesis: Using SystemVerilog for ASIC and FPGA Design

SystemVerilog for Verification

Pong Chu's Books

Digital Design and Computer Architecture

Xilinx University's Workshop Labs

Intel Workshops

Intel Tutorials