Reddit reviews Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them
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That's a pretty shallow approach... Don't judge a [language] by it's [syntax].
Just look at this StackOverflow question; the general consensus seems to be that you should learn VHDL first due to there being less weirdness and the compiler catching more mistakes.
One person even says that the similarity of Verilog to C is actually a disadvantage, as the similarity is only skin-deep and can mislead you, whereas:
>VHDL was different enough that I found it much easier to think in terms of logic design and not control flow.
Just realize that books like Verilog and SystemVerilog Gotchas: 101 Common Coding Errors and How to Avoid Them exist.
This article is also interesting.