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So I'm super late for this

So assuming you know about address translation, which memory level do you mean? One not found in L1-L3 cache, having a cache miss and going to DRAM/Main Memory, or going to larger and slower system memory?

Those three levels consist of SRAM, DRAM, and then Nand flash or Magnetic Disk?

These data requests go through each level as a miss, and with any memory there is a controller. In your basic arch class when you talked about Cache, once the cache controller addressed the appropriate tag bits and data located. You can look at an
SRAM https://upload.wikimedia.org/wikipedia/commons/3/31/SRAM_Cell_(6_Transistors).svg cell to get an idea of what the transistor layout of cache looks like. I suppose another way to look at a cache cell is like a D Flip Flop, just holding the data. The controller signals the array/pulses the array that holds the data, which outputs from the appropriate location.

In general think of it as a bunch of DFFs combined with output gates, and a simple control logic circuit. The DFFs are in an array, the output tristate buffers that hold the data are appropriately signaled, given an enable pin request to the DFF and an output pin signal to the Tristate. That's really simplified though. In this super abstract thought process, you can assume the control logic to be some standard FSM, corresponding to some sequential circuit, consisting of transistors. The DFF again is a 6 transistor register essentially, and the tristate is a however many transistor setup.

I'd recommend looking at this course by Bruce Jacob, a prominent researcher in Memory Systems Architecture
and this [book] (http://www.elsevier.com/books/memory-systems/jacob/978-0-12-379751-3) also by him. That book is a systems perspective (architects) on Cache, DRAM and Disk. Highly recommend the book to any Architect.

Additonally, for a more IC based perspective you can look at this book, which has an accompayning course on cmosedu.com.

Sorry I don't really have a TLDR, since there are multiple levels of memory, and I can't give a generalized tofu memory array since it doesn't really describe any practical or real system for a transistor level understanding.

Hope this helps and I'm sorry if I've been speaking pseudoscience and this is all wrong, I don't claim to be correct!

A quick search found http://www.amazon.com/Modern-Processor-Design-Fundamentals-Superscalar/dp/1478607831 as well as http://www.ebay.com/itm/like/111520297055?lpid=82
I have no idea what their contents are though, or if they cover what you are looking for